Discrete Fourier Transform Algorithms for Bit-Serial, GaAs Processor Architectures
Discrete Fourier Transform Algorithms for
Bit-Serial, GaAs Processor Architectures
Systems and Processes Engineering Corp.
1406 Smith Road, Suite A
Austin, TX 78721
Gary B. McMillian (512-385-0082)
GSFC -- NAS5-30291
An innovative array processor architecture for computing Fourier transforms and
other commonly used signal processing algorithms is under development. During Phase
I, an architecture was designed to extract the highest possible array performance
from state-of-the-art, gallium arsenide (GaAs) technology. The architectural design
features a high-performance, reduced-instruction-set-computer (RISC) processor implemented
in GaAs, a floating-point coprocessor, and a unique array communications coprocessor
also implemented in GaAs.
The architecture includes very high speed, low-gate-count, bit-serial arithmetic,
and communication units in the floating-point and communication coprocessors, respectively.
Utilizing the very high speed of GaAs, currently with clock rates in excess of 1
GHz, bit-serial units can be used to form the core of complex arithmetic and communication
units. A bit-serial architecture is, in fact, ideal for implementation of the communication
links between processors.
Potential Commercial Application:
Potential Commercial Application: Potential applications are mainly in signal processing,
with possible application to computational physics and artificial intelligence. The
GaAs RISC processors will also find application in high-performance graphics work