VORAGO Technologies has produced an IC definition and architecture for a rad-hard I/O Expansion chip that is capable of interfacing to next generation spaceflight processor devices including the High-Performance Spaceflight Computing (HPSC) chiplet.
We have gathered the best available knowledge of HPSC use-cases to conceptualize and articulate the requirements for an I/O Expansion Chip, creating an architecture for an optimized and robust IC that can be implemented to meet the requirements of next generation NASA space electronics systems.
In addition to providing a perfect companion IC to the HPSC in next generation systems architectures, the I/O Expansion Chip can facilitate the use of the HPSC with legacy systems (such as those that include MIL-STD-1553 communications). Support of legacy systems is a practical requirement for the next decade. The I/O Expansion Chip will allow the HPSC to interface with legacy systems as well as next generation systems. We most recently added USB 3.0 to the definition to support camera interfaces that are being considered / selected for Orion and SPLICE programs at NASA Johnson Space Center.
VORAGO Technologies would like to commercialize the I/O Expansion Chip product and target sales to NASA and non-NASA commercial aerospace customers. Making the product commercially successful outside of NASA applications will increase sales volume and establish a more robust supply chain for the product.
In phase II, we propose to create a detailed IC specification, acquire the main IP blocks and create a hardware prototype system of the I/O Chip using the Synopsys HAPS80 prototyping system. This approach is consistent with that taken for the HPSC chiplet development process.
The I/O Expansion Chip will be suitable for use in spacecraft, and cyber-physical/robotics or autonomous systems in space radiation environments. Everywhere that an HPSC device can be used, it is likely that one or more I/O Expansion Chips can be used. Such applications include: Vision-based algorithms with real-time requirements (e.g. landing with hazard avoidance), Model-based reasoning techniques for autonomy (e.g. Mars rover mission planning), High rate instrument data processing (e.g. high-resolution satellite image processing)
I/O Expansion for processors & FPGAs, Multi-comms interface & hub for processors & FPGAs, Network bridge for processors/FPGAs, Standalone A5 class processor with multiple comms interfaces, Redundant processor system for implementing system-level low power modes, Redundant processor system for implementing failsafe, Interface to cameras on Orion and SPLICE programs that use USB 3.0 camera interface