NASA SBIR 2017 Solicitation

FORM B - PROPOSAL SUMMARY


PROPOSAL NUMBER: 17-2 Z6.01-8732
PHASE 1 CONTRACT NUMBER: NNX17CP47P
SUBTOPIC TITLE: High Performance Space Computing Technology
PROPOSAL TITLE: FLASHRAD: A Non-Volatile 3D Rad Hard Memory Module for High Performance Space Computers

SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Irvine Sensors Corporation
3001 Red Hill Avenue, B3-108
Costa Mesa, CA 92626 - 4506
(714) 444-8700

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
James S Yamaguchi
jyamaguchi@irvine-sensors.com
3001 Red Hill Avenue, B3-108
Costa Mesa, CA 92626 - 4506
(714) 444-8785

CORPORATE/BUSINESS OFFICIAL (Name, E-mail, Mail Address, City/State/Zip, Phone)
Mr. Daryl L Smetana
dsmetana@irvine-sensors.com
3001 Red Hill Avenue, B3-108
Costa Mesa, CA 92626 - 4506
(714) 444-8760

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 3
End: 4

Technology Available (TAV) Subtopics
High Performance Space Computing Technology is a Technology Available (TAV) subtopic that includes NASA Intellectual Property (IP). Do you plan to use the NASA IP under the award?
No

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)

The computing capabilities of onboard spacecraft are a major limiting factor for accomplishing many classes of future missions. Although technology development efforts are underway that will provide improvements to spacecraft CPUs, they do not address the limitations of current onboard memory systems. In addition to CPU upgrades, effective execution of data-intensive operations such as terrain relative navigation, hazard detection and avoidance, autonomous planning and scheduling, and onboard science data processing and analysis require high-bandwidth, high-capacity memory systems to maximize data storage and provide rapid access to observational data captured by high-data-rate instruments (e.g., Hyperspectral Infrared Imager, Interferometric Synthetic Aperture Radar).

Three-dimensional ICs, after a long wait, are now a reality. The first mainstream products are 3D memory cubes that offer manifold improvements in size, capacity, speed, and power. Unfortunately, none of these are ready for space. The purpose of this research and development is to pursue a non-volatile, 3D memory module that can meet the high-reliability requirements of space and interface to the High Performance Space Computer (HPSC) using a high-speed serial interface. Development will include fabricating a 3D memory cube and RTL for a FPGA based memory controller which will eventually be migrated to a rad-hard ASIC.  The FPGA based platform will integrate a 3D memory cube to produce a 3D memory module prototype that will validate and demonstrate the features, reliability, and performance of the envisioned 3D module.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
The computing capabilities of onboard spacecraft are a major limiting factor for accomplishing many classes of future missions. Although technology development efforts are underway that will provide improvements to spacecraft CPUs, they do not address the limitations of current onboard memory systems. In addition to CPU upgrades, effective execution of data-intensive operations such as terrain relative navigation, hazard detection and avoidance, autonomous planning and scheduling, and onboard science data processing and analysis require high-bandwidth, high-capacity memory systems to maximize data storage and provide rapid access to observational data captured by high-data-rate instruments (e.g., Hyperspectral Infrared Imager, Interferometric Synthetic Aperture Radar).Three-dimensional ICs, after a long wait, are now a reality. The first mainstream products are 3D memory cubes that offer manifold improvements in size, capacity, speed, and power. Unfortunately, none of these are ready for space. The purpose of this research and development is to pursue a non-volatile, 3D memory module that can meet the high-reliability requirements of space and interface to the High Performance Space Computer (HPSC) using a high-speed serial interface. Development will include fabricating a 3D memory cube and RTL for a FPGA based memory controller which will eventually be migrated to a rad-hard ASIC. The FPGA based platform will integrate a 3D memory cube to produce a 3D memory module prototy

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Optimization of the logic base of a memory cube has not been available for any application. Development of the design tools to achieve better optimization of these logic bases will in turn lead to a broader application base which will benefit not only the users for space applications, but will benefit terrestrial users to help improve the efficiency of their electronics by addressing SWaP issues.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)
Circuits (including ICs; for specific applications, see e.g., Communications, Networking & Signal Transport; Control & Monitoring, Sensors)
Manufacturing Methods
Materials (Insulator, Semiconductor, Substrate)
Metallics
Models & Simulations (see also Testing & Evaluation)
Processing Methods
Software Tools (Analysis, Design)
Spacecraft Instrumentation & Astrionics (see also Communications; Control & Monitoring; Information Systems)

Form Generated on 03-05-18 17:24