NASA SBIR 2017 Solicitation


PROPOSAL NUMBER: 171 S1.04-8720
SUBTOPIC TITLE: Sensor and Detector Technology for Visible, IR, Far IR and Submillimeter
PROPOSAL TITLE: Wafer level Integration on PolyStrata(R) Interposer (WIPI) (17013)

SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Nuvotronics, Inc.
7586 Old Peppers Ferry Loop
Radford, VA 24141 - 8846
(800) 341-2333

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
Dr. Jean-Marc Rollin
2305 Presidential Drive
Durham, NC 27703 - 0000
(800) 341-2333 Extension :113

CORPORATE/BUSINESS OFFICIAL (Name, E-mail, Mail Address, City/State/Zip, Phone)
Mr. Scott Meller
7586 Old Peppers Ferry Loop
Radford, VA 24141 - 8846
(800) 341-2333 Extension :124

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 2
End: 3

Technology Available (TAV) Subtopics
Sensor and Detector Technology for Visible, IR, Far IR and Submillimeter is a Technology Available (TAV) subtopic that includes NASA Intellectual Property (IP). Do you plan to use the NASA IP under the award?

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
Nuvotronics will develop a robust wafer-level integration technology using our proprietary PolyStrata interposer to enable high-frequency interconnects and routing between two dis-similar substrates: silicon, SiGe, GaAs, GaN, InP wafers. The PolyStrata passives grown on the wafers will consist of high performance interconnects capable of aligning and soldering the two wafers using copper pillars to create a Ball Grid Array (BGA). Establishing novel wafer-to-wafer push fit technologies will demonstrate sub 5psec interconnection delay between technologies. With integration of low loss routing between the technologies, our proposed interposer can monolithically integrate passives such as high Q inductors, filters, resonators directly between the two wafers. The PS interposer offers an excellent structure to improve the CTE mismatch between wafers and enable thermal heat piping to direct the heat away from the different stack. In Ph I, Nuvotronics will demonstrate the integration of GaAs on Silicon using the PS interposer technology. The goal: to integrate a 1"x1" GaAs and Silicon die, demonstrating interface loss < 0.3dB and sub 5psec interconnection delay. The design will integrate CTE compensation structure to enable over 100C of temperature variation. Nuvotronics will design and optimize the interface between PolyStrata and silicon, and between GaAs and PolyStrata, to minimize stress and improve mm-wave RF performance. Next, Nuvotronics will fabricate a surrogate silicon and surrogate GaAs wafer with PolyStrata interface. A solder ball back-end process will be applied to both wafer technology and integration of solder balls. The 4" wafers will be diced in 1"x1" dies before being integrated. DC and RF measurements will demonstrate electrical performance. Preliminary temp. cycling will be performed to demonstrate reliability of the interface. In Ph II, Nuvotronics will demonstrate 4-inch wafer level integration and performance under temp. cycling.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Nuvotronics is committed to transitioning the proposed technology to NASA applications for future phased arrays and more integrated RF systems. Our involvement in 3 NASA IIP awards and 2 Phase IIE projects in combination with 2 additional prime contractor/government sponsored efforts for space borne instruments (totaling over $12M) will help reduce risk in transitioning the proposed technology to NASA space platforms.

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
The technology developed can be leveraged in commercial phased array for the next generation 5G network. In this new mm-wave domain, the challenges of creating microwave circuits become exponentially harder. PolyStrata technology offers a revolutionary solution by compartmentalizing all of the microwave "challenges" into a single integrated component, placed on a standard printed circuit board.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)
Manufacturing Methods
Microelectromechanical Systems (MEMS) and smaller
Microfabrication (and smaller; see also Electronics; Mechanical Systems; Photonics)

Form Generated on 04-19-17 12:59