NASA SBIR 2010 Solicitation


PROPOSAL NUMBER: 10-1 X6.02-9897
SUBTOPIC TITLE: Radiation Hardened/Tolerant and Low Temperature Electronics and Processors
PROPOSAL TITLE: Innovative Columnar Type of Grid Array SJ BIST HALT Method

SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Ridgetop Group, Inc.
6595 North Oracle Road
Tucson, AZ 85704 - 5645
(520) 742-3300

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
James Hofmeister
6595 North Oracle Road
Tucson, AZ 85704 - 5645
(520) 742-3300

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 2
End: 5

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
Ridgetop will develop a superior method for testing and qualifying columnar type of grid arrays such as field programmable gate arrays (FPGAs) packaged in column grid array (CGA) and ceramic column grid array (CCGA) packages using any type of manufacturing process.
The proposed innovation is an electrical test method that utilizes unassigned CGA or CCGA package pins as dedicated monitoring pins, with a dedicated Solder Joint Built-in-Self Test (SJ BIST) program in the FPGA. SJ BIST operates in real-time to detect faults, with zero false alarms, in those connections. Supporting software provides a visual status of the state-of-health of each pair of monitored pins.
At the end of the Phase 1, there will be a prototype HALT definition, a modified SJ BIST firmware designed specifically for use in HALTs (as opposed to being subjected to HALT for evaluation), a designed board with FPGAs programmed with the modified SJ BIST firmware, a prototype software program to support SJ BIST HALTs, at least two electronic boards fabricated and populated for use in developing and testing the software program.
At the end of the Phase 2, the usefulness and accuracy of SJ BIST HALT will have been proven by the running of the defined HALT regimes. And by working with industry representatives, SJ BIST HALT will be ready for commercialization by government agencies, by suppliers of electronic boards to government agencies, by commercial firms.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
An SJ BIST-based HALT will be a very useful tool to increase the reliability of electronic boards with FPGA packages on the boards, to reduce costs for any firm that performs HALTs of completed electronic boards. This includes NASA and DoD prime and subprime contractors such as BAE Platform Systems, Goodrich, Lockheed Martin, Raytheon, Northrop Grumman, Boeing and NASA.
NASA and non-NASA commercial applications will benefit from the following:
• Improved manufacturing reliability by using a HALT simulation program to provide early evaluation results.
• Materials and processes can be evaluated in less time at much reduced cost compared to running the defined HALT.
• A proposed HALT regime consisting of single or multiple steps of both thermal and vibration cycling can be evaluated for probable effectiveness prior to implementation and running of the HALT.

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Commercial firms that use HALTs include automotive manufacturers and major suppliers such as Daimler, General Motors, Ford and Chrysler.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)
Analytical Methods
Circuits (including ICs; for specific applications, see e.g., Communications, Networking & Signal Transport; Control & Monitoring, Sensors)
Detectors (see also Sensors)
In Situ Manufacturing
Lifetime Testing
Nondestructive Evaluation (NDE; NDT)
Software Tools (Analysis, Design)
Tools/EVA Tools
Verification/Validation Tools

Form Generated on 09-03-10 12:12