|PROPOSAL NUMBER:||05-II O1.06-9806|
|PHASE-I CONTRACT NUMBER:||NNC06CA60C|
|SUBTOPIC TITLE:||Reconfigurable/Reprogrammable Communication Systems|
|PROPOSAL TITLE:||A Hardware/Software Design Environment for Reconfigurable Communication Systems|
SMALL BUSINESS CONCERN
(Firm Name, Mail Address, City/State/Zip, Phone)
2130 Chandler Lane
Glenview, IL 60026-5744
PRINCIPAL INVESTIGATOR/PROJECT MANAGER
(Name, E-mail, Mail Address, City/State/Zip, Phone)
2130 Chandler Lane
Glenview, IL 60026-5744
TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically develop flexible, reconfigurable communications systems. We will develop automated compiler algorithms to translate software code available in a variety of high level languages (C/C++/SIMULINK) and assembly of various general purpose processors into Register Transfer Level VHDL code to be mapped onto FPGA-based hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. We will demonstrate our concepts using a prototype compiler that will translate software implementations of communications applications into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA and a Digilent XUP FPGA board. The proposed work is revolutionary and addresses NASA's Space Exploration needs as follows: (1) it will develop a system level tool for designing hardware systems which will reduce design times from months to days (2) it will enable the use of cost-efficient, high-performance FPGAs (3) it will allow engineers to reuse of millions of lines of software developed in the past for general purpose processors, and migrate them painlessly to newer SOC platforms.
POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
NASA's missions are quite diverse ranging from (1) Satellite imaging to study Global Climate Modeling (2) Scanning Deep Space using the Hubble Space Telescope (3) Building the International Space Station to perform various experiments in space (4) Using the Space Shuttle to carry payloads to the ISS and carry on various space experiments (5) Exploring the Solar System in projects such as the Mars Exploration Rover, and the VAULT telescope to take pictures of the Sun. (6) Searching for extra-solar planets using transit photometry in the VULCAN Camera Project. All these projects have one thing in common; they require a lot of sophisticated image processing operations on images captured by various cameras. FPGAs are being used for a variety of image processing tasks in numerous NASA applications. The BINACHIP compiler will be useful in developing hardware designs on these FPGA based hardware applications.
POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
The software that will be developed by BINACHIP will have two general application areas (1) embedded systems software (2) electronic design automation. Increasing demands for cell-phones, PDAs, and network devices have provided opportunities for the growth of embedded software, operating systems and development tools vendors. The embedded systems software market is expected to become $21 billion in 2005. As newer processor architectures are announced, there is a need to reuse and migrate the software from older generation processors to newer processors. The BINACHIP compiler will be useful to these companies to assist in the task of software migration. The second commercial area for BINACHIP is electronic design automation (EDA) that is expected to become a $6 billion market in 2005. One of these segments is that of system level EDA, which is expected to grow to at least $300 million by 2005. The BINACHIP compiler will enable translation of software from a general-purpose processor onto a system-on-chip consisting of processors, memories and FPGAs.
|NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.|
TECHNOLOGY TAXONOMY MAPPING
Software Development Environments